VLSI: 2-4 Decoder Dataflow Modelling with Testbench
Verilog Code for 2-4 Decoder Dataflow Modelling
module decoder_2_to_4(
input a0,
input a1,
output d0,
output d1,
output d2,
output d3
);
assign an0 = ~ a0;
assign an1 = ~ a1;
assign d0 = an0 & an1;
assign d1 = a0 & an1;
assign d2 = an0 & a1;
assign d3 = a0 & a1;
endmodule
//Testbench code for 2-4 Decoder Dataflow Modelling
initial begin
//
Initialize Inputs
a0
= 0;a1 = 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;
a0=1;a1=0;
#100;
a0=0;a1=1;
#100;
a0=1;a1=1;
end
Output:
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