VLSI: BCD to Excess 3 Converter Dataflow Modelling with Testbench

Verilog Code for BCD to Excess 3 Dataflow Modelling

module bcd_ex3(

    input a,

    input b,

    input c,

    input d,

    output w,

    output x,

    output y,

    output z

    );

              assign w = (a | (b & c) | (b & d));

              assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d)));

              assign y = ((c & d) | ((~c) & (~d)));

              assign z = ~d;

endmodule

//Testbench code for BCD to Excess 3 Dataflow Modelling

initial begin

                             // Initialize Inputs

                             a = 0;

                             b = 0;

                             c = 0;

                             d = 0;                  

            // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100; a = 0; b = 0; c = 1; d = 1;

                                #100; a = 0; b = 1; c = 0; d = 1;                      

 end