VLSI: 4 Bit Full Adder Dataflow Modelling with Testbench
Verilog Code for 4 Bit Full Adder Dataflow Modelling
module four_bit_full_adder(
input [3:0]a,b,
input c,
output [3:0]sum,
output carry,
);
fulladder f0(sum[0],c0,a[0],b[0],c);
fulladder f1(sum[1],c1,a[1],b[1],c0);
fulladder f2(sum[2],c2,a[2],b[2],c1);
fulladder f3(sum[3],carry,a[3],b[3],c2);
endmodule
module fulladder(sum,carry,a,b,c4);
output sum,carry;
input a,b,c4;
assign p = (a^b);
assign r = a & b;
assign sum = p ^ c4;
assign q = p ^ c4;
assign carry = q ^ r;
endmodule
//Testbench code for 4 Bit Full Adder Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;b = 0;c = 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;
a = 0;b = 0;c = 1;
#100;
a = 0;b = 1;c = 0;
#100;
a = 0;b = 1;c = 1;
#100;
a = 1;b = 0;c = 0;
#100;
a = 1;b = 0;c = 1;
#100;
a = 1;b = 1;c = 0;
#100;
a = 1;b = 1;c = 1;
end
Output:
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