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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
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module bcd_ex3_Dataflow(
input a,
input b,
input c,
input d,
output w,
output x,
output y,
output z
);
assign w = (a | (b & c) | (b & d));
assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d)));
assign y = ((c & d) | ((~c) & (~d)));
assign z = ~d;
endmodule
Excess 3 to BCD:
module ex3_to_bcd(
input w,
input x,
input y,
input z,
output a,
output b,
output c,
output d
);
assign a = ((w & x) | (w & y & z));
assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z));
assign c = (((~y) & z) | (y & (~z)));
assign d = ~z;
endmodule
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