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VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100;
VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Verilog: 8 to 1 MUX Behavioral Modelling using Verilog Case Statement with Testbench Code
Verilog Code for 8 to 1 MUX Behavioral Modelling using Verilog Case Statement with Testbench Code module 8_1_MUX( input [7:0]i, input s2,s1,s0, output out ); reg out; always @ (i or s2 or s1 or s0) case ({s2,s1,s0}) 0 : out = I[0]; 1 : out = I[1]; 2 : out = I[2]; 3 : out = I[3]; 4 : out = I[4]; 5 : out = I[5]; 6 : out = I[6]; 7 : out = I[7]; default : out = 1’bx; endcase endmodule //Testbench code for 8 to 1 MUX (Multiplexer) Behavioral Modelling using Verilog Case Statement initial begin // Initialize Inputs i=8’b 10101010; s2=0; s1=0; s0=0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s2=0; s1=0; s0=1; #100; s2=0; s1=1; s0=0; #100; s2=0; s1=1; s0=1; #100; s2=1; s1=0; s0=0; #100; s2=1; s1=0; s0=1; #100; s2=1; s1=1; s0=0; #100; s2=1; s1=1; s0=1; end initial begin #100 $monitor (“I=%b, s2=%b, s1=%b, s0=%b, out=%b”, I, s2, s1, s0, out); end endmodule Xillinx Out
VLSI: 2 Bit Magnitude Comparator Dataflow Modelling
module mag_comp2bit( input a0, input a1, input b0, input b1, output p, // p = (a < b) output r, // r = (a > b) output q // q = (a = b) ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming