VLSI: 1-2 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
1-2 Demultiplexer Verilog Code:
module DEMUX_1_to_2(input s,
input d,
output y0,
output y1
);
assign sn = ~ s;
assign y0 = sn & d;
assign y1 = s & d;
endmodule
//Testbench Code
initial begin// Initialize Inputs
s = 0;
d = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s=0;d=1;
#100; s=1;d=0;
#100; s=1;d=1;
End
Output:
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