Verilog: Half Subtractor Structural/Gate Level Modelling with Testbench

Verilog Code for Half Subtractor Structural/Gate Level Modelling

module half_subtractor(

    input i0,

    input i1,

    output d,

    output b,

     wire in0

    );

not (in0,i0);

xor(d,i0,i1);

and(b,in0,i1);

endmodule

//Testbench code for Half Subtractor Structural/Gate Level Modelling

initial begin

                             // Initialize Inputs

                             i0 = 0;

                             i1 = 0;

                             // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100; i0 = 0; i1 = 1;

                             #100; i0 = 1; i1 = 0;

                             #100; i0 = 1; i1 = 1;

end

Output:

RTL Schematic:

Half Subtractor Verilog