Latest Post

Ads

Verilog: Half Subtractor Structural/Gate Level Modelling with Testbench

-

Verilog Code for Half Subtractor Structural/Gate Level Modelling

module half_subtractor(
    input i0,
    input i1,
    output d,
    output b,
     wire in0
    );
not (in0,i0);
xor(d,i0,i1);
and(b,in0,i1);
endmodule


//Testbench code for Half Subtractor Structural/Gate Level Modelling


initial begin
                             // Initialize Inputs
                             i0 = 0;
                             i1 = 0;
                             // Wait 100 ns for global reset to finish
                             #100;
                             // Add stimulus here
                             #100; i0 = 0; i1 = 1;
                             #100; i0 = 1; i1 = 0;
                             #100; i0 = 1; i1 = 1;
end


Output:


RTL Schematic:
Half Subtractor Verilog



Comments

Post a Comment

Ads

Popular posts from this blog

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

-
Image
module bcd_ex3_Dataflow(     input a,     input b,     input c,     input d,     output w,     output x,     output y,     output z     ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd(     input w,     input x,     input y,     input z,     output a,     output b,     output c,     output d     ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Read more

Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench

-
Image
Verilog Code for Full Subtractor Structural/Gate Level Modelling module  full_sub(borrow,diff,a,b,c); output  borrow,diff; input  a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial  begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of  Verilog Programming
Read more

VLSI: 4-1 MUX Dataflow Modelling with Testbench

-
Image
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin                              // Initialize Inputs                              a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;                              // Wait 100 ns for global reset to finish                              #100;                              // Add stimulus here                              #100; s0=0;s1=1;a=0;b=1;c=0;d=0;                              #100; s0=1;s1=0;a=0;b=0;c=1;d=0;                           
Read more

VLSI: Half Subtractor and Full Subtractor Gate Level Modelling

-
Image
Half Subtractor: Verilog Module Code: module half_subtractor (      input  a,      input  b,      output  diff       output  borr ); wire x; xor (diff,a,b); not (x,a); and (borr,x,b); endmodule Full Subtractor: Verilog Module Code: module full_subtractor (      input  a,      input  b,      input  c,      output  diff       output  borr ); wire x,n2,z,n1; xor s1(x,a,b); not s3(n2,x); not s4(n1,c); and s5(y,n1,b); xor s2(diff,a,x); and s6(z,n2,a); or (borr,y,z); endmodule
Read more

VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench

-
Image
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs                              d = 1;                              s0 = 0;                              s1 = 0;                              // Wait 100 ns for global reset to finish                              #100;                   
Read more