VLSI: Excess 3 to BCD Converter Dataflow Modelling with Testbench

Verilog Code for Excess 3 to BCD Dataflow Modelling

module ex3_bcd(

    input w,

    input x,

    input y,

    input z,

    output a,

    output b,

    output c,

    output d

    );

              assign  a = ((w & x) | (w & y & z));

              assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z));

              assign c = (((~y) & z) | (y & (~z)));

              assign d = ~z;

endmodule

//Testbench code for Excess 3 to BCD Dataflow Modelling

initial begin

                             // Initialize Inputs

                             w = 0;

                             x = 0;

                             y = 0;

                             z = 0;                  

            // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100; w = 0; x = 0; y = 1; z = 1;

                             #100; w = 0; x = 1; y = 0; z = 1;                   

 end