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VLSI: Half Subtractor and Full Subtractor Gate Level Modelling

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Half Subtractor:

Verilog Module Code:

module half_subtractor(
    input a,
    input b,
    output diff 
    output borr);
wire x;
xor (diff,a,b);
not (x,a);
and (borr,x,b);
endmodule

Full Subtractor:

Verilog Module Code:

module full_subtractor(
    input a,
    input b,
    input c,
    output diff 
    output borr);
wire x,n2,z,n1;
xor s1(x,a,b);
not s3(n2,x);
not s4(n1,c);
and s5(y,n1,b);
xor s2(diff,a,x);
and s6(z,n2,a);
or (borr,y,z);

endmodule

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