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Verilog: Gray to Binary Converter Structural/Gate Level Modelling with Testbench

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Verilog Code for Gray to Binary Structural/Gate Level Modelling

module gray_to_binary(
    input g0,
    input g1,
    input g2,
    input g3,
    output b0,
    output b1,
    output b2,
    output b3
    );
               buf(b0,g0);
               xor(b1,g0,g1),(b2,g0,g1,g2),(b3,g0,g1,g2,g3);
endmodule

//Testbench code for Gray to Binary Structural/Gate Level Modelling

initial begin
// Initialize Inputs
g0 = 0;g1 = 0;g2 = 0;g3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#50;g0 = 0;g1 = 0;g2 = 0;g3 = 1;
#50;g0 = 0;g1 = 0;g2 = 1;g3 = 0;
#50;g0 = 0;g1 = 0;g2 = 1;g3 = 1;
#50;g0 = 0;g1 = 1;g2 = 0;g3 = 0;
#50;g0 = 0;g1 = 1;g2 = 0;g3 = 1;
#50;g0 = 0;g1 = 1;g2 = 1;g3 = 0;
#50;g0 = 0;g1 = 1;g2 = 1;g3 = 1;
#50;g0 = 1;g1 = 0;g2 = 0;g3 = 0;
#50;g0 = 1;g1 = 0;g2 = 0;g3 = 1;
#50;g0 = 1;g1 = 0;g2 = 1;g3 = 0;
#50;g0 = 1;g1 = 0;g2 = 1;g3 = 1;
#50;g0 = 1;g1 = 1;g2 = 0;g3 = 0;
#50;g0 = 1;g1 = 1;g2 = 0;g3 = 1;
#50;g0 = 1;g1 = 1;g2 = 1;g3 = 0;
#50;g0 = 1;g1 = 1;g2 = 1;g3 = 1;
end

Output:
Verilog Gray to Binary Converter
Verilog Gray to Binary Converter Resonse

Other Verilog Programs:

Go to Index of Verilog Programming

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