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Verilog: Half Adder Structural/Gate Level Modelling with Testbench

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Verilog Code for Half Adder Structural/Gate Level Modelling

module half_adder(
    input i0,
    input i1,
    output s,
    output c
    );
               and(c,i0,i1);
               xor(s,i0,i1);
endmodule

//Testbench code for Half Adder Structural/Gate Level Modelling


initial begin
                             // Initialize Inputs
                             i0 = 0;
                             i1 = 0;
                             // Wait 100 ns for global reset to finish
                             #100;
                             // Add stimulus here
                             #100; i0 = 0; i1 = 1;
                             #100; i0 = 1; i1 = 0;
                             #100; i0 = 1; i1 = 1;
end


Output:


RTL Schematic:
Half Adder Verilog

Other Verilog Programs:

Go to Index of Verilog Programming

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