VLSI: 4 Bit Full Subtractor Structural/Gate Level Modelling with Testbench
Verilog Code for 4 Bit Full Subtractor Structural/Gate Level Modelling
module fus(borrow,diff,a,b,c);
output borrow,diff;
input a,b,c;
wire w1,w4,w5,w6;
xor (diff,a,b,c);
not n1(w1,a);
and a1(w4,w1,b);
and a2(w5,w1,c);
and a3(w6,b,c);
or o1(borrow,w4,w5,w6);
endmodule
//Testbench code for 4 Bit Full Subtractor Structural/Gate Level Modelling
initial begin
end
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