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VLSI: 4 Bit Full Subtractor Structural/Gate Level Modelling with Testbench

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Verilog Code for 4 Bit Full Subtractor Structural/Gate Level Modelling

module full_subtractor_4_bit(
    input [3:0]a,b,
    input bin,
    output [3:0]diff,
    output borrow,
               wire c0,c1,c2
    );
               fus f0(diff[0],c0,a[0],b[0],bin);
               fus f1(diff[1],c1,a[1],b[1],c0);
               fus f2(diff[2],c2,a[2],b[2],c1);
               fus f3(diff[3],borrow,a[3],b[3],c2);
endmodule


module fus(borrow,diff,a,b,c);

output borrow,diff;

input a,b,c;

wire w1,w4,w5,w6;

xor (diff,a,b,c);

not n1(w1,a);

and a1(w4,w1,b);

and a2(w5,w1,c);

and a3(w6,b,c);

or o1(borrow,w4,w5,w6);

endmodule

//Testbench code for 4 Bit Full Subtractor Structural/Gate Level Modelling

initial begin
                             // Initialize Inputs
                             a = 0;
                             b = 0;
                             bin = 0;
                             // Wait 100 ns for global reset to finish
                             #100;
                             // Add stimulus here
                             #100;a=0;b=0;bin=1;
                             #100;a=0;b=1;bin=0;
                             #100;a=0;b=1;bin=1;
                             #100;a=1;b=0;bin=0;
                             #100;a=1;b=0;bin=1;
                             #100;a=1;b=1;bin=0;
                            #100;a=1;b=1;bin=1;
end


Output:






Other Verilog Programs:

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