VLSI: AND Gate Dataflow Modelling with Testbench
Verilog Code for AND gate Dataflow Modelling
module ANDgate(
input a,
input b,
output c
);
assign c = a & b;
endmodule
//Testbench code for AND gate Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;b = 0;
// Wait 100
ns for global reset to finish
#100
a = 0; b = 1;
#100
a = 1; b = 0;
#100
a = 1; b = 1;
end
Output:
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