Stellar Coding - Verilog, Filter Design and more..

This is a solution guide to the exercises of the book "The Solution Manual of the Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar". Following are the Solutions to  Solution Manual on Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar , exercises of all chapters in the book.    Chapter 1  ----------------- No Exercises ----------------  Chapter 2 :  Hierarchical Modeling Concepts  Chapter 3 :  Basic Concepts  Chapter 4 :  Modules and Ports  Chapter 5:  Gate-level Modeling  Chapter 6 :  Dataflow Modeling  Chapter 7 : Behavioral Modeling  Chapter 8 :  Tasks and Functions Download Solution Manual:  Click on this link (Mega.nz Link) [Solution Manual to Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar] Preview of Solution Manual: For Verilog Programs: Go to Index of  Verilog Programming Tags: Verilog HDL solution by samir palnitkar, verilog hdl is used to design VLSI circuits, solution manual to verilog hdl b

Verilog Code for D Flip Flop Dataflow Modelling module DFF( input d, input en, output q, output qb );   assign a = ( en & ( ~ d )); assign b = ( en & d ); assign q = ~ ( a | qb ); assign qb = ~ ( b | q ); endmodule   //Testbench initial begin // Initialize Inputs d = 0; en = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100;d = 0;en = 1; #100;d = 1;en = 0; #100;d = 1;en = 1;   end Xillinx Output: D Flip Flop Dataflow Modelling     Also See: List of Verilog Programs

Verilog Code for T Flip Flop Dataflow Modelling module TFF( input t, input en, output q, output qb );   assign a = ~ ( qb & t & en ); assign b = ~ ( q & t & en ); assign q = ~ ( qb & a ); assign qb = ~ ( b & q & ( ~ t ) ); endmodule   //Testbench initial begin // Initialize Inputs   t = 0; en = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100;t = 1;en = 0; #100;t = 0;en = 1; #100;t = 1;en = 1;   end Xillinx Output: T Flip Flop Dataflow Modelling     Also See: List of Verilog Programs

    Verilog Code for 1 Bit Magnitude Comparator Dataflow Modelling module comparator_1_bit( input x, input y, output a, //x>y output b, //x=y output c //x<y ); assign xn = ~ x; assign yn = ~ y; assign a = x & yn; assign c = xn & y; assign b = ~ ( a | c );  endmodule   //Testbench initial begin // Initialize Inputs x = 0;y = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100; x=0;y=1; #100; x=1;y=0; #100; x=1;y=1;   end Xillinx Output: 1 Bit Magnitude Comparator Dataflow Modelling     Also See: List of Verilog Programs

  Verilog Code for 1 to 2  DeMultiplexer Dataflow Modelling module DEMUX_1_to_2( input s, input d, output y0, output y1 ); assign sn = ~ s; assign y0 = sn & d; assign y1 = s & d; endmodule   //Testbench initial begin // Initialize Inputs s = 0; d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s=0;d=1; #100; s=1;d=0; #100; s=1;d=1;    end Xillinx Output: 1-2 DEMUX Verilog Coding     Also See: List of Verilog Programs

  Verilog Code for 8 to 1 Multiplexer Dataflow Modelling module mux_8to1(     input a, input b, input c, input D0, input D1, input D2, input D3, input D4, input D5, input D6, input D7, output out, ); module m81( output out, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2); assign S1bar=~S1; assign S0bar=~S0; assign S2bar=~S2; assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & S0) | (D2 & S2bar & S1 & S0bar) + (D3 & S2bar & S1 & S0) + (D4 & S2 & S1bar & S0bar) + (D5 & S2 & S1bar & S0) + (D6 & S2 & S1 & S0bar) + (D7 & S2 & S1 & S0); endmodule //Testbench code for 8-1 MUX Dataflow Modelling initial begin // Initialize Inputs a= 0;b = 0;c = 0;D0 = 1;D1 = 0;D2 = 0;D3 = 0;D4 = 0;D5 = 0;D6 = 0;D7 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1;d0 = 0;d1 = 1;d2 =