VLSI: Half Subtractor Dataflow Modelling with Testbench

Verilog Code for Half Subtractor Dataflow Modelling

module half_subtractor(

    input i0,

    input i1,

    output d,

    output b,

     wire in0

    );

assign in0 = ~ i0;

assign d = i0 ^ i1;

assign b = in0 & i1;

endmodule

//Testbench code for Half Subtractor Dataflow Modelling

initial begin

                             // Initialize Inputs

                             i0 = 0;

                             i1 = 0;

                             // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100; i0 = 0; i1 = 1;

                             #100; i0 = 1; i1 = 0;

                             #100; i0 = 1; i1 = 1;

 end

Output: