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Verilog: 8-3 Encoder Structural/Gate Level Modelling with Testbench

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Verilog Code for 8-3 Encoder Structural/Gate Level Modelling

module encoder_8_to_3(
    input d0,
    input d1,
    input d2,
    input d3,
    input d4,
    input d5,
    input d6,
    input d7,
    output q0,
    output q1,
    output q2
    );
or (q0,d1,d3,d5,d7),(q1,d2,d3,d6,d7),(q2,d4,d5,d6,d7);
endmodule

//Testbench code for 8-3 Encoder Structural/Gate Level Modelling

initial begin
        // Initialize Inputs
               d0 = 1;
               d1 = 0;
               d2 = 0;
               d3 = 0;
               d4 = 0;
               d5 = 0;
               d6 = 0;
               d7 = 0;
         // Wait 100 ns for global reset to finish
               #100;
        // Add stimulus here
    #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 1;d6 = 0;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 1;d7 = 0;
    #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 1;
end

Output:
Verilog 8-3 Encoder
Verilog 8-3 Encoder Response

Other Verilog Programs:

Go to Index of Verilog Programming

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