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Verilog: NAND Gate Behavioral Modelling with Testbench Code
Verilog Code NAND Gate Behavioral Modelling module NAND_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==1 & b==1) out = 1’b0; else out = 1’b1; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: NAND Gate Verilog Code Behavioral Modelling
Verilog: AND Gate Behavioral Modelling with Testbench Code
Verilog Code AND Gate Behavioral Modelling module AND_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==1 & b==1) out = 1’b1; else out = 1’b0; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: AND Gate Behavioral Response
Verilog: OR Gate Behavioral Modelling with Testbench Code
Verilog Code OR Gate Behavioral Modelling module OR_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==0 & b==0) out = 1’b0; else out = 1’b1; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: OR Gate Response
Applied Instrumentation GTU (Sem-1) - ME Instrumentation and Control (IC)
1. STUDY MATERIAL for Applied Instrumentation GTU (Sem-1) - ME Instrumentation and Control (IC) SEM 1: Subjects: AIDC (Advanced Industrial Drives and Control) ISC (Intelligent Systems and Control) OTE (Optimization Techniques for Engineers) ESI (Embedded System for Instrumentation) IPR Click on the below given links to download study material: Syllabus Books Notes Study Material Lab Manual Question Papers Assignments Sem 2: ME - Applied Instrumentation Click on the below given link to download study material: Sem 2 Folder Subjects: AVD (Advanced Verilog Design) ISI (Intelligent Sensors and Instrumentation) DC (Digital Control) ASPE (Advanced Signal Processing and Estimation) Disaster Management Also See: Optimization Techniques in C Verilog Programming Filter Designing
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VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
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VLSI: 4-1 MUX Dataflow Modelling with Testbench
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Verilog: 4 Bit Counter Behavioral Modelling using If Else Statement
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Verilog: 4 to 1 Multiplexer Behavioral Modelling with Testbench Code
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VLSI: 3-8 Decoder Dataflow Modelling with Testbench
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