VLSI: 4-1 MUX Structural/Gate Level Modelling with Testbench
Verilog Code for 4-1 MUX Structural/Gate Level Modelling
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4-1 MUX
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module m41(out, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);
and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule//Testbench code for 4-1 MUX Structural/Gate Level Modelling
initial begin// Initialize Inputs
a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s0=0;s1=1;a=0;b=1;c=0;d=0;
#100; s0=1;s1=0;a=0;b=0;c=1;d=0;
#100; s0=1;s1=1;a=0;b=0;c=0;d=1;end
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