Verilog: 1 to 2 DEMUX (Demultiplexer) Structural/Gate Level Modelling with Testbench

Verilog Code for 1-2 DEMUX Structural/Gate Level Modelling

1-2 DEMUX

module DEMUX_1_to_2(
    input s,
    input d,
    output y0,
    output y1
    );
not(sn,s);
and(y0,sn,d);
and(y1,s,d);
endmodule

//Testbench code for 1-2 DEMUX Structural/Gate Level Modelling

initial begin
// Initialize Inputs
         s = 0;
         d = 0;
// Wait 100 ns for global reset to finish
         #100;
// Add stimulus here
#100; s=0;d=1;
#100; s=1;d=0;
#100; s=1;d=1;
end

Output:

Verilog 1-2 DEMUX Response

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