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VLSI: 1 Bit Magnitude Comparator Structural/Gate Level Modelling with Testbench

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Verilog Code for 1 Bit Comparator Structural/Gate Level Modelling

module comparator_1_bit(
    input x,
    input y,
    output a,  //x>y
    output b,  //x=y
    output c   //x<y
    );
not(xn,x),(yn,y);
and(a,x,yn),(c,xn,y);
nor(b,a,c);
endmodule
//Testbench code for 1 Bit Comparator Structural/Gate Level Modelling
initial begin
// Initialize Inputs
x = 0;y = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; x=0;y=1;
#100; x=1;y=0;
#100; x=1;y=1;
end

Magnitude Comparator
Output:
Verilog 1 Bit Magnitude Comparato
Verilog 1 Bit Magnitude Comparator Response

Other Verilog Programs:

Go to Index of Verilog Programming


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