VLSI: NOT gate Dataflow Modelling with Testbench
Verilog Code for NOT gate Dataflow Modelling
module NOTgate(
input a,
output c
);
assign c = ~a;
endmodule
//Testbench code for NOT gate Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;
// Wait 100
ns for global reset to finish
#100
a = 0;
#100
a = 1;
end
Output:
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