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VLSI: Binary to Gray Dataflow Modelling with Testbench

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Verilog Code for Binary to Gray Dataflow Modelling

module binary_to_gray(
    input b1,
    input b2,
    input b3,
    input b4,
    output g1,
    output g2,
    output g3,
    output g4
    );
assign g1 = b1;
assign g2 = b1 ^ b2;
assign g3 = b2 ^ b3;
assign g4 = b3 ^ b4;
endmodule

//Testbench code for Binary to Gray Dataflow Modelling

initial begin
                             // Initialize Inputs
                             b1 = 0;b2 = 0;b3 = 0;b4 = 0;
                             // Wait 100 ns for global reset to finish
                             #100;
                             // Add stimulus here
                             #100;b1 = 0;b2 = 0;b3 = 0;b4 = 1;
                             #100;b1 = 0;b2 = 0;b3 = 1;b4 = 0;
                             #100;b1 = 0;b2 = 0;b3 = 1;b4 = 1;
                             #100;b1 = 0;b2 = 1;b3 = 0;b4 = 0;
                             #100;b1 = 0;b2 = 1;b3 = 0;b4 = 1;
                             #100;b1 = 0;b2 = 1;b3 = 1;b4 = 0;
                             #100;b1 = 0;b2 = 1;b3 = 1;b4 = 1;
                             #100;b1 = 1;b2 = 0;b3 = 0;b4 = 0;
                             #100;b1 = 1;b2 = 0;b3 = 0;b4 = 1;
                             #100;b1 = 1;b2 = 0;b3 = 1;b4 = 0;
                             #100;b1 = 1;b2 = 0;b3 = 1;b4 = 1;
                             #100;b1 = 1;b2 = 1;b3 = 0;b4 = 0;
                             #100;b1 = 1;b2 = 1;b3 = 0;b4 = 1;
                             #100;b1 = 1;b2 = 1;b3 = 1;b4 = 0;
                             #100;b1 = 1;b2 = 1;b3 = 1;b4 = 1;

 end


Ouutput:
VLSI: Binary to Gray Dataflow Modelling with Testbench




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