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Verilog: Full Adder Structural/Gate Level Modelling with Testbench

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Verilog Code for Full Adder Structural/Gate Level Modelling

module full_adder(
    input a,
    input b,
    input cin,
    output s,
    output cout,
               wire p,q,r
    );
xor(p,a,b);
and(r,a,b);
xor(sum,p,cin);
and(q,p,cin);
or(cout,q,r);
endmodule


//Testbench code for Full Adder Structural/Gate Level Modelling


initial begin
                             // Initialize Inputs
                             a = 0;b = 0;cin = 0;
                             // Wait 100 ns for global reset to finish
                             #100;
                             // Add stimulus here
                             #100; a = 0;b = 0;cin = 1;
                             #100; a = 0;b = 1;cin = 0;
                             #100; a = 0;b = 1;cin = 1;
                             #100; a = 1;b = 0;cin = 0;
                             #100; a = 1;b = 0;cin = 1;
                             #100; a = 1;b = 1;cin = 0;
                             #100; a = 1;b = 1;cin = 1;
end


Output:


RTL Schematic:
Full Adder Verilog

Other Verilog Programs:

Go to Index of Verilog Programming

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