VLSI: Gray to Binary Dataflow Modelling with Testbench

Verilog Code for Gray to Binary Dataflow Modelling

module gray_to_binary(

    input g0,

    input g1,

    input g2,

    input g3,

    output b0,

    output b1,

    output b2,

    output b3

    );

         assign b0 = g0;buf(b0,g0);

         assign b1 = g0 ^ g1;

assign b2 = g0 ^ g1 ^ g2;

assign b3 = g0 ^ g1 ^ g2 ^ g3;

endmodule

//Testbench code for Gray to Binary Dataflow Modelling

initial begin

                             // Initialize Inputs

                             g0 = 0;g1 = 0;g2 = 0;g3 = 0;

                             // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #50;g0 = 0;g1 = 0;g2 = 0;g3 = 1;

                             #50;g0 = 0;g1 = 0;g2 = 1;g3 = 0;

                             #50;g0 = 0;g1 = 0;g2 = 1;g3 = 1;

                             #50;g0 = 0;g1 = 1;g2 = 0;g3 = 0;

                             #50;g0 = 0;g1 = 1;g2 = 0;g3 = 1;

                             #50;g0 = 0;g1 = 1;g2 = 1;g3 = 0;

                             #50;g0 = 0;g1 = 1;g2 = 1;g3 = 1;

                             #50;g0 = 1;g1 = 0;g2 = 0;g3 = 0;

                             #50;g0 = 1;g1 = 0;g2 = 0;g3 = 1;

                             #50;g0 = 1;g1 = 0;g2 = 1;g3 = 0;

                             #50;g0 = 1;g1 = 0;g2 = 1;g3 = 1;

                             #50;g0 = 1;g1 = 1;g2 = 0;g3 = 0;

                             #50;g0 = 1;g1 = 1;g2 = 0;g3 = 1;

                             #50;g0 = 1;g1 = 1;g2 = 1;g3 = 0;

                             #50;g0 = 1;g1 = 1;g2 = 1;g3 = 1;

 end

Output: