VLSI: 3-8 Decoder Dataflow Modelling with Testbench
Verilog Code for 3-8 Decoder Dataflow Modelling
module decoder3_to_8(
input x,
input y,
input z,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
assign d0 = xn & yn & zn;
assign d1 = xn & yn & z;
assign d2 = xn & y & zn;
assign d3 = xn & y & z;
assign d4 = x & yn & z;
assign d5 = x & yn & z;
assign d6 = x & y & zn;
assign d7 = x & y & z;
assign xn = ~ x;
assign yn = ~ y;
assign zn = ~ z;
endmodule
//Testbench code for 3-8 Decoder Dataflow Modelling
initial begin
//
Initialize Inputs
x
= 0;y = 0;z = 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;x
= 0;y = 0;z = 1;
#100;x
= 0;y = 1;z = 0;
#100;x
= 0;y = 1;z = 1;
#100;x
= 1;y = 0;z = 0;
#100;x
= 1;y = 0;z = 1;
#100;x
= 1;y = 1;z = 0;
#100;x
= 1;y = 1;z = 1;
end
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