VLSI: 4-2 Encoder Dataflow Modelling with Testbench

Verilog Code for 4-2 Encoder Dataflow Modelling

module encode_4_to_2(

    input d0,d1,d2,d3,

    output a0,a1

    );

assign x = ~ d2;

assign y = x & d1;

assign a0 = y | d3;

assign a1 = d2 | d3;

endmodule

//Testbench code for 4-2 Encoder Dataflow Modelling

initial begin

                             // Initialize Inputs

                             d0 = 1;d1 = 0;d2 = 0;d3 = 0;

                             // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;

                             #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;

                             #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;

 end

Output: