Latest Post
VLSI: XNOR Gate Dataflow Modelling with Testbench
- Get link
- X
- Other Apps
Verilog Code for XNOR gate Dataflow Modelling
module XNORgate(
input a,
input b,
output c
);
assign c = ~ (a ^ b);
endmodule
//Testbench code for XNOR gate Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;b = 0;
// Wait 100
ns for global reset to finish
#100
a = 0; b = 1;
#100
a = 1; b = 0;
#100
a = 1; b = 1;
end
- Get link
- X
- Other Apps
Comments
Post a Comment