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1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench

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Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling

1-4 DEMUX
1-4 DEMUX
module demux_1_to_4(
    input d,
    input s0,
    input s1,
    output y0,
    output y1,
    output y2,
    output y3
    );
not(s1n,s1),(s0n,s0);
and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1);
endmodule

//Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling

initial begin
// Initialize Inputs
        d = 1;
        s0 = 0;
        s1 = 0;
// Wait 100 ns for global reset to finish
       #100;

// Add stimulus here
    #100;d = 1;s0 = 1;s1 = 0;
    #100;d = 1;s0 = 0;s1 = 1;
    #100;d = 1;s0 = 1;s1 = 1;
end


Output:
Verilog 1-4 DEMUX
Verilog 1-4 DEMUX Verilog Code Response

Other Verilog Programs:

Go to Index of Verilog Programming

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