VLSI: NAND Gate Dataflow Modelling with Testbench
Verilog Code for NAND gate Dataflow Modelling
module NANDgate(
input a,
input b,
output c
);
assign c = ~ (a & b);
endmodule
//Testbench code for NAND gate Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;b = 0;
// Wait 100
ns for global reset to finish
#100
a = 0; b = 1;
#100
a = 1; b = 0;
#100
a = 1; b = 1;
Output:
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