Verilog: NOT gate Structural/Gate Level Modelling with Testbench
Verilog Code for NOT gate Structural/Gate Level Modelling
module NOTgate(
input a,
output c
);
not(c,a);
endmodule
//Testbench code for NOT gate Structural/Gate Level Modelling
initial begin
// Initialize
Inputs
a
= 0;
// Wait 100 ns
for global reset to finish
#100
a = 0;
#100
a = 1;
end
Output:
RTL Schematic:
 |
| Not Gate Verilog |
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