Stellar Coding - Verilog, Filter Design and more..

Verilog Code for 3 to 8 Decoder Behavioral Modelling using Case Statement with Testbench Code module 3_8_DEC(      input [3:0]din,      output [7:0]dout      ); reg [7:0]dout; always @ (din) case (din)     0 : dout[0] = 1;       1 : dout[1] = 1;       2 : dout[2] = 1;       3 : dout[3] = 1;       4 : dout[4] = 1;       5 : dout[5] = 1;       6 : dout[6] = 1;       7 : dout[7] = 1;      default : dout = 8’bxxxxxxxx; endcase endmodule //Testbench code for 3 to 8 Decoder Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100; din=0;  #100; din=1;  #100; din=2;  #100; din=3; #100; din=4; #100; din=5;  #100; din=6;  #100; din=7;  end initial begin  #100   $monitor (“ din=%b, dout=%b”, din, dout);  end  endmodule Xillinx Output: 3 - 8 Decoder Behavioral Modelling Response

Verilog Code for 8 to 1 MUX Behavioral Modelling using Verilog Case Statement with Testbench Code module 8_1_MUX(      input [7:0]i,      input s2,s1,s0,      output out      ); reg out; always @ (i or s2 or s1 or s0) case ({s2,s1,s0})     0 : out = I[0];       1 : out = I[1];       2 : out = I[2];       3 : out = I[3];       4 : out = I[4];       5 : out = I[5];      6 : out = I[6];       7 : out = I[7];      default : out = 1’bx; endcase endmodule //Testbench code for 8 to 1 MUX (Multiplexer) Behavioral Modelling using Verilog Case Statement initial  begin // Initialize Inputs   i=8’b 10101010; s2=0; s1=0; s0=0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s2=0; s1=0; s0=1;  #100; s2=0; s1=1; s0=0;  #100; s2=0; s1=1; s0=1; #100; s2=1; s1=0; s0=0;  #100; s2=1; s1=0; s0=1;  #100; s2=1; s1=1; s0=0;  #100; s2=1; s1=1; s0=1; end initial begin  #100   $monitor (“I=%b, s2=%b, s1=%b, s0=%b, out=%b”, I, s2, s1, s0, out);  end  endmodule Xillinx Out

Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code module 1_4_DEMUX(      input i,     input s1, s0,      output [3:0]out      ); reg [3:0]out; always @ (i or s0 or s1) case ({s1,s0})     0: out0 = i;     1: out1 = i;     2: out2 = i;     3: out3 = i;     default: out = 4'bxxxx; endcase endmodule //Testbench code for 1 to 4 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   i = 1;s1 = 0;s0 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100; s1=0; s0=1;  #100; s1=1; s0=0; #100; s1=1; s0=1;  end initial begin  #100 ; $monitor (“I=%b, s1=%b, s0=%b, out=%b”, I, s1, s0, out); end endmodule 

Verilog Code for 1 to 8 DEMUX Behavioral Modelling using Case Statement with Testbench Code module 1_8_DEMUX(      input i,     input s2, s1, s0,      output [7:0]out      ); reg [7:0]out; always @ (i or s0 or s1 or s2) case ({s2,s1,s0})     0: out0 = i;     1: out1 = i;     2: out2 = i;     3: out3 = i;     4: out4 = i;     5: out5 = i;     6: out6 = i;     7: out7 = i;     default: out = 8'bxxxxxxx; endcase endmodule //Testbench code for 1 to 8 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   i = 1;s2 = 0;s1 = 0;s0 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s2=0; s1=0; s0=1; #100; s2=0; s1=1; s0=0; #100; s2=0; s1=1; s0=1; #100; s2=1; s1=0; s0=0;  #100; s2=1; s1=0; s0=1;  #100; s2=1; s1=1; s0=0;  #100; s2=1; s1=1; s0=1;   end initial begin  #100 ; $monitor (“I=%b, s2=%b, s1=%b, s0=%b, out=%b”, I, s2, s1, s0, out); end endmodule  Output: 1 to 8 DEMUX Response

Verilog Code for 1 to 2 DEMUX Behavioral Modelling using Case Statement with Testbench Code module 1_2_DEMUX(      input i0,     input s0,     output out1,       output out2      ); always @ (i0 or s0) case (s0)     0: out1 = i0;     1: out2 = i0;     default: out1 = 1'bx;out2 = 1'bx; endcase endmodule //Testbench code for 1 to 2 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   i0 = 1;s0 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s0 = 1; #100; s0 = 0; end Output: 1-2 DeMUX Response

Verilog Code for 2 to 1 MUX Behavioral Modelling using Case Statement with Testbench Code module 2_1_MUX(      input i0,      input i1,     input s0,       output out      ); always @ (i0 or i1 or s0) case (s0)     0: out = i0;     1: out = i1;     default: out = 1'bx; endcase endmodule //Testbench code for 2 to 1 MUX (Multiplexer)Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   i0 = 1;i1 = 1;s0 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s0 = 0; #100; s0 = 1; end Output: 2 - 1 MUX Behavioral Modelling Response

Verilog Code 4-1 Multiplexer Behavioral Modelling using Case Statement module Mux_4to1 ( input [3:0] i, input s1, s0, output out ); always @(i or s1 or s0) case({s1, s0}) 0 : out = i[0]; 1 : out = i[1]; 2 : out = i[2]; 3 : out = i[3]; default : out = 1’bx; endcase endmodule // test-bench initial begin i=1'b1010; s1=0; s0=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 s1 = 0; s0= 1; #100 s1 = 1; s0= 0; #100 s1 = 1; s0= 1; end

  Verilog Code Full Adder Behavioral Modelling module Full_Adder ( input a, b, cin; output sum, carry ); always @(a or b or cin) assign {carry,sum} = a + b + cin; endmodule // test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; cin=1; #100 a=1; b=0; cin=1; #100 a=1; b=1; cin=1; end initial begin #100 $ monitor (“a=%b, b=%b, cin=%b, sum=%b, carry=%b”, a, b, cin, sum, carry); end endmodule Xilinx Output: Verilog code for Full Adder Behavioral Modelling