VLSI: 8-1 MUX Structural/Gate Level Modelling with Testbench
Verilog Code for 8-1 MUX Structural/Gate Level Modelling
 |
| 8-1 MUX |
module mux_8to1(
input a,
input b,
input c,
input d0,
input d1,
input d2,
input d3,
input d4,
input d5,
input d6,
input d7,
output out,
wire an,bn,cn,t1,t2,t3,t4,t5,t6,t7,t8
);
not(an,a),(bn,b),(cn,c);
and(t1,an,bn,cn,d0),(t2,an,bn,c,d1),(t3,an,b,cn,d2),(t4,an,b,c,d3),(t5,a,bn,cn,d4),(t6,a,bn,c,d5),(t7,a,b,cn,d6),(t8,a,b,c,d7);
not(out,t1,t2,t3,t4,t5,t6,t7,t8);
endmodule//Testbench code for 8-1 MUX Structural/Gate Level Modelling
initial begin// Initialize Inputs
a = 0;b = 0;c = 0;d0 = 1;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;// Wait 100 ns for global reset to finish#100;
// Add stimulus here
#100; a = 0;b = 0;c = 1;d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100; a = 0;b = 1;c = 0;d0 = 0;d1 = 0;d2 = 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100; a = 0;b = 1;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100; a = 1;b = 0;c = 0;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;d7 = 0;
#100; a = 1;b = 0;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 1;d6 = 0;d7 = 0;
#100; a = 1;b = 1;c = 0;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 1;d7 = 0;
#100; a = 1;b = 1;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 1;end
 |
Verilog 8-1 MUX ResponseOther Verilog Programs:Go to Index of Verilog Programming |
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