Verilog Code for 1 to 8 DEMUX with Testbench Code
Verilog Code for 1-8 DEMUX Structural/Gate Level Modelling
module demux_1_to_8(
input d,
input s0,
input s1,
input s2,
output y0,
output y1,
output y2,
output y3,
output y4,
output y5,
output y6,
output y7 );
not (s0n,s0),(s1n,s1),(s2n,s2);
and (y0,d,s0n,s1n,s2n),(y1,d,s0,s1n,s2n),(y2,d,s0n,s1,s2n),(y3,d,s0,s1,s2n),(y4,d,s0n,s1n,s2),(y5,d,s0,s1n,s2),(y6,d,s0n,s1,s2),(y7,d,s0,s1,s2);
endmodule//Testbench code for 1-8 DEMUX Structural/Gate Level Modelling
initial begin
// Initialize Inputs
d = 0;s0 = 0;s1 = 0;s2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; d = 1;s0 = 0;s1 = 0;s2 = 0;
#100; d = 1;s0 = 1;s1 = 0;s2 = 0;
#100; d = 1;s0 = 0;s1 = 1;s2 = 0;
#100; d = 1;s0 = 1;s1 = 1;s2 = 0;
#100; d = 1;s0 = 0;s1 = 0;s2 = 1;
#100; d = 1;s0 = 1;s1 = 0;s2 = 1;
#100; d = 1;s0 = 0;s1 = 1;s2 = 1;
#100; d = 1;s0 = 1;s1 = 1;s2 = 1;end
Output:
 |
Verilog/VLSI 1-8 DEMUX ResponseOther Verilog Programs:Go to Index of Verilog Programming |
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