VLSI: Full Subtractor Dataflow Modelling with Testbench

Verilog Code for Full Subtractor Dataflow Modelling

module full_subtractor(borrow, diff, a, b, c);

output borrow, diff;

input a, b, bin;

assign x = a ^ b ;
assign y = (~x) & bin ;
assign z = (~a) & b ;

assign diff = x ^ bin ;
assign borrow = y | z ;

endmodule

//Testbench code for Full Subtractor Dataflow Modelling

initial begin

                             // Initialize Inputs

                             a = 0;

                             b = 0;

                             bin = 0;

                             // Wait 100 ns for global reset to finish

                             #100;

                             // Add stimulus here

                             #100; a = 0;b = 0;bin = 1;

                             #100; a = 0;b = 1;bin = 0;

                             #100; a = 0;b = 1;bin = 1;

                             #100; a = 1;b = 0;bin = 0;

                             #100; a = 1;b = 0;bin = 1;

                             #100; a = 1;b = 1;bin = 0;

                             #100; a = 1;b = 1;bin = 1;

 end

Output: