VLSI: Half Adder Dataflow Modelling with Testbench
Verilog Code for Half Adder Dataflow Modelling
module half_adder(
input i0,
input i1,
output s,
output c
);
assign c = i0 & i1;
assign s = i0 ^ i1;
endmodule
//Testbench code for Half Adder Dataflow Modelling
initial begin
//
Initialize Inputs
i0 = 0;
i1
= 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;
i0 = 0; i1 = 1;
#100;
i0 = 1; i1 = 0;
#100;
i0 = 1; i1 = 1;
end
Output:
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