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C Program for Level Sketch
C Level Sketch: #include<stdio.h> #include<conio.h> #include<math.h> int main() { float th,ov, HH,H,L,LL,lowTap,UpTap,CC,HH1,H1,L1,LL1,HHper,Hper,Lper,LLper,BtTap; char ch; do { printf("\nEnter Tank Height in mm:"); scanf("%f",&th); printf("\nHeight of HH:"); scanf("%f",&HH); printf("\nHeight of H:"); scanf("%f",&H); printf("\nHeight of L:"); scanf("%f",&L); printf("\nHeight of LL:"); scanf("%f",&LL); printf("\nEnter Height of Overflow Nozzle (if required):"); scanf("%f",&ov); if (ov != 0) { th = ov; } else { th = th; } printf("Height Valid: %.2f",th); HHper = (HH * 100)/th; Hper = (H * 100)/th; Lper = (L * 100)/th; LLper = (LL * 100)/th; if (HHper < 90 && LLper > 10) { ...
Sun - The Ball of Fire
Mysterious Sun: Electromagnetic winds emmited from Sun are solar winds. Solar winds consists of protons and electrons, when these protons and electrons interact with Earth's magnetic field sky get lit up by different colors. The solar winds are emmited by solar holes in sun, as these solar holes are less dense than other parts of Sun, they provide path to allow the wind outwards to surface of Sun. These winds are thrown out by such a huge force that they can travel very long distances, even reaching to Earth. These winds can have speed up to 1000 Km/sec. Solar Emission Even though we know Sun from centuries, there are many mysteries of Sun remained unsolved. Most popular mystery is regarding Corona of Sun. Corona is outer layer of Sun's atmosphere. Corona is hotter than the inner layer Chromosphere. Sun's visible surface Photosphere has temperature 5800°C. Outer layer of Photosphere is Chromosphere. Temperature of Chromosphere is estimated to be 4000°C....
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Samir Palnitkar Solution Manual Free Download PDF of Verilog HDL
This is a solution guide to the exercises of the book "The Solution Manual of the Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar". Following are the Solutions to Solution Manual on Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar , exercises of all chapters in the book. Chapter 1 ----------------- No Exercises ---------------- Chapter 2 : Hierarchical Modeling Concepts Chapter 3 : Basic Concepts Chapter 4 : Modules and Ports Chapter 5: Gate-level Modeling Chapter 6 : Dataflow Modeling Chapter 7 : Behavioral Modeling Chapter 8 : Tasks and Functions Download Solution Manual: Click on this link (Mega.nz Link) [Solution Manual to Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar] Preview of Solution Manual: For Verilog Programs: Go to Index of Verilog Programming Tags: Verilog HDL solutio...
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
VLSI: 8-3 Encoder Dataflow Modelling with Testbench
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3( input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, output q0, output q1, output q2 ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin ...
VLSI: 3-8 Decoder Dataflow Modelling with Testbench
Verilog Code for 3-8 Decoder Dataflow Modelling module decoder3_to_8( input x, input y, input z, output d0, output d1, output d2, output d3, output d4, output d5, output d6, output d7 ); assign d0 = xn & yn & zn; assign d1 = xn & yn & z; assign d2 = xn & y & zn; assign d3 = xn & y & z; assign d4 = x & yn & z; assign d5 = x & yn & z; assign d6 = x & y & zn; assign d7 = x & y & z; assign xn = ~ x; assign yn = ~ y; assign zn = ~ z; endmodule //Testbench code for 3-8 Decoder Dataflow Modelling ...
Verilog: 4 - 2 Encoder Structural/Gate Level Modelling with Testbench
Verilog Code for 4-2 Encoder Structural/Gate Level Modelling module encode_4_to_2( input d0,d1,d2,d3, output a0,a1 ); wire x,y,z; not g1(x,d2); and g2(y,x,d1); or g3(a0,y,d3); or g4(a1,d2,d3); endmodule //Testbench code for 4-2 Encoder Structural/Gate Level Modelling initial begin // Initialize Inputs d0 = 1;d1 = 0;d2 = 0;d3 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0; #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1; end Output: Verilog 4-2 Encoder Response Other Verilog Programs: Go to Index of Verilog Programming