Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling
module full_sub(borrow,diff,a,b,c);
output borrow,diff;
input a,b,c;
wire w1,w4,w5,w6;
xor (diff,a,b,c);
not n1(w1,a);
and a1(w4,w1,b);
and a2(w5,w1,c);
and a3(w6,b,c);
or o1(borrow,w4,w5,w6);
endmodule//Testbench code for Full Subtractor Structural/Gate Level Modelling
initial begin// Initialize Inputs
a = 0;
b = 0;
c = 0;// Wait 100 ns for global reset to finish#100;
// Add stimulus here
#100; a = 0;b = 0;c = 1;
#100; a = 0;b = 1;c = 0;
#100; a = 0;b = 1;c = 1;
#100; a = 1;b = 0;c = 0;
#100; a = 1;b = 0;c = 1;
#100; a = 1;b = 1;c = 0;
#100; a = 1;b = 1;c = 1;end
Output:
RTL Schematic:
 |
| Full Subtractor Verilog |
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