VLSI: Full Adder Dataflow Modelling with Testbench
Verilog Code for Full Adder Dataflow Modelling
module full_adder(
input a,
input b,
input cin,
output s,
output cout,
);
assign x = a ^ b ;
assign y = x & cin ;
assign z = a & b ;
assign y = x & cin ;
assign z = a & b ;
assign s = x ^ cin ;
assign cout = y | z ;
assign cout = y | z ;
endmodule
//Testbench code for Full Adder Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 0;b = 0;cin = 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;
a = 0;b = 0;cin = 1;
#100;
a = 0;b = 1;cin = 0;
#100;
a = 0;b = 1;cin = 1;
#100;
a = 1;b = 0;cin = 0;
#100;
a = 1;b = 0;cin = 1;
#100;
a = 1;b = 1;cin = 0;
#100;
a = 1;b = 1;cin = 1;
end
Output:
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