Verilog Code for AND gate with Testbench
Verilog Code for AND gate Structural/Gate Level Modelling
module ANDgate(
input a,
input b,
output c
);
and(c,a,b);
endmodule
input a,
input b,
output c
);
and(c,a,b);
endmodule
//Testbench code for AND gate Structural/Gate Level Modelling
initial begin
end
Output:
RTL Schematic:
 |
| AND Gate Verilog |
Other Verilog Programs:
Go to Index of Verilog Programming
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