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Verilog: 4 - 2 Encoder Structural/Gate Level Modelling with Testbench

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Verilog Code for 4-2 Encoder Structural/Gate Level Modelling

module encode_4_to_2(
    input d0,d1,d2,d3,
    output a0,a1
    );
wire x,y,z;
not g1(x,d2);
and g2(y,x,d1);
or g3(a0,y,d3);
or g4(a1,d2,d3);
endmodule
//Testbench code for 4-2 Encoder Structural/Gate Level Modelling
initial begin
// Initialize Inputs
 d0 = 1;d1 = 0;d2 = 0;d3 = 0;
// Wait 100 ns for global reset to finish
 #100;
// Add stimulus here
 #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;
 #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;
 #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;
end

 Output:
Verilog 4-2 Encoder
Verilog 4-2 Encoder Response

Other Verilog Programs:

Go to Index of Verilog Programming

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