VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling
module m41(out, i0, i1, i2, i3, s0, s1);
output out;
input i0, i1, i2, i3, s0, s1;
assign y0 = (i0
& (~s0) & (~s1));
assign y1 = (i1
& (~s0) & s1);
assign y2 = (i2
& s0 & (~s1));
assign y3 = (i3
& s0 & s1);
assign out = (y0 |
y1 | y2 | y3);
endmodule
//Testbench code for 4-1 MUX Dataflow Modelling
initial begin
//
Initialize Inputs
a
= 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;
// Wait 100
ns for global reset to finish
#100;
// Add
stimulus here
#100;
s0=0;s1=1;a=0;b=1;c=0;d=0;
#100;
s0=1;s1=0;a=0;b=0;c=1;d=0;
#100;
s0=1;s1=1;a=0;b=0;c=0;d=1;
end
Output:
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