Verilog: OR gate Structural/Gate Level Modelling with Testbench

Verilog Code for OR gate Structural/Gate Level Modelling

module ORgate(

    input a,

    input b,

    output c

    );

or(c,a,b);

endmodule

//Testbench code for OR gate Structural/Gate Level Modelling

initial begin

              // Initialize Inputs

              a = 0;b = 0;

              // Wait 100 ns for global reset to finish

              #100 a = 0; b = 1;

              #100 a = 1; b = 0;

              #100 a = 1; b = 1;

end

Output:

RTL Schematic:

OR Gate Verilog

Other Verilog Programs:

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