Verilog: Binary to Gray Converter Structural/Gate Level Modelling with Testbench
Verilog Code for Binary to Gray Structural/Gate Level Modelling
module binary_to_gray(
input b1,
input b2,
input b3,
input b4,
output g1,
output g2,
output g3,
output g4
);
buf(g1,b1);
xor (g2,b1,b2),(g3,b2,b3),(g4,b3,b4);
endmodule
//Testbench code for Binary to Gray Structural/Gate Level Modelling
// Initialize Inputsinitial begin
b1 = 0;b2 = 0;b3 = 0;b4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100;b1 = 0;b2 = 0;b3 = 0;b4 = 1;
#100;b1 = 0;b2 = 0;b3 = 1;b4 = 0;
#100;b1 = 0;b2 = 0;b3 = 1;b4 = 1;
#100;b1 = 0;b2 = 1;b3 = 0;b4 = 0;
#100;b1 = 0;b2 = 1;b3 = 0;b4 = 1;
#100;b1 = 0;b2 = 1;b3 = 1;b4 = 0;
#100;b1 = 0;b2 = 1;b3 = 1;b4 = 1;
#100;b1 = 1;b2 = 0;b3 = 0;b4 = 0;
#100;b1 = 1;b2 = 0;b3 = 0;b4 = 1;
#100;b1 = 1;b2 = 0;b3 = 1;b4 = 0;
#100;b1 = 1;b2 = 0;b3 = 1;b4 = 1;
#100;b1 = 1;b2 = 1;b3 = 0;b4 = 0;
#100;b1 = 1;b2 = 1;b3 = 0;b4 = 1;
#100;b1 = 1;b2 = 1;b3 = 1;b4 = 0;
#100;b1 = 1;b2 = 1;b3 = 1;b4 = 1;end
Output:
 |
Verilog Binary to Gray Converter Response Other Verilog Programs:Go to Index of Verilog Programming |
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