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Verilog: Half Subtractor Behavioral Modelling with Testbench Code
Verilog Code Half Subtractor Behavioral Modelling module Half_Sub ( input a, b; output diff, borr ); always @(a or b) assign {borr,diff} = (~a) + b; endmodule // test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, diff=%b, borr=%b”, a, b, diff, borr); end endmodule Xilinx Output: Half Subtractor Behavioral Modelling Verilog Code
Verilog: Half Adder Behavioral Modelling with Testbench Code
Verilog Code Half Adder Behavioral Modelling module Half_Adder ( input a, b; output sum, carry ); always @(a or b) assign {carry,sum} = a + b; endmodule // test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, sum=%b, carry=%b”, a, b, sum, carry); end endmodule Xilinx Output: Half Adder Verilog Code Behavioral Modelling
Full Subtractor Verilog Code in Behavioral Modelling with Testbench Code
Full Subtractor Verilog Code in Behavioral Modelling module Full_Sub ( input a, b, bin; output diff, borr ); always @(a or b or bin) assign {borr,diff} = (~a) + b + bin; endmodule // test-bench initial begin a=0; b=0; bin=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; bin=0; #100 a=1; b=0; bin=0; #100 a=1; b=1; bin=0; end initial begin #100 $ monitor (“a=%b, b=%b, bin=%b, diff=%b, borr=%b”, a, b, bin, diff, borr); end endmodule Xilinx Output: Full Subtractor Verilog Code Behavioral Modelling
Verilog: XNOR Gate Behavioral Modelling with Testbench Code
Verilog Code XNOR Gate Behavioral Modelling module XNOR_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==b) out = 1’b1; else out = 1’b0; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: Verilog XNOR Gate Behavioral Modelling Response
Verilog: XOR Gate Behavioral Modelling with Testbench Code
Verilog Code XOR Gate Behavioral Modelling module XOR_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==b) out = 1’b0; else out = 1’b1; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: XOR Gate Verilog Behavioral Modelling
Verilog: NOR Gate Behavioral Modelling with Testbench Code
Verilog Code NOR Gate Behavioral Modelling module NOR_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==0 & b==0) out = 1’b1; else out = 1’b0; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: NOR Gate Behavioral Modelling Verilog
Verilog: NOT Gate Behavioral Modelling with Testbench Code
Verilog Code NOT Gate Behavioral Modelling // main module NOT_GATE ( input a; output out ); reg out; always @(a) begin if (a==0) out = 1’b1; else out = 1’b0; endmodule // test-bench initial begin a=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; #100 a=1; end initial begin #100 $ monitor (“a=%b, out=%b”, a, out); end endmodule Xilinx Output: Not Gate Behavioral Modelling
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VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100;
VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
VLSI: 2 Bit Magnitude Comparator Dataflow Modelling
module mag_comp2bit( input a0, input a1, input b0, input b1, output p, // p = (a < b) output r, // r = (a > b) output q // q = (a = b) ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming