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VLSI: 2-1 MUX Structural/Gate Level Modelling with Testbench

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Verilog Code for 2-1 MUX Structural/Gate Level Modelling

module two_to_1_mux(
output Y,
input D0, D1, S,
wire T1, T2, Sbar
    );
and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);
endmodule

//Testbench code for 2-1 MUX Structural/Gate Level Modelling

initial begin




                             // Initialize Inputs
                             S = 0; D0 = 0; D1 = 0;
                             // Wait 100 ns for global reset to finish
                             #100;

                             // Add stimulus here
                             #100; S = 0;D0 = 0;D1 = 1;
                             #100; S = 0;D0 = 1;D1 = 0;
                             #100; S = 0;D0 = 1;D1 = 1;
                             #100; S = 1;D0 = 0;D1 = 0;
                             #100; S = 1;D0 = 0;D1 = 1;
                             #100; S = 1;D0 = 1;D1 = 0;
                             #100; S = 1;D0 = 1;D1 = 1;
end

 Output:

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