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Verilog: 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code

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Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code

module 4_2_ENC(
    input [3:0]din,
    output [1:0]dout  
    );
reg [1:0]dout; 
always @ (din) 
case (din)
    1 : dout[0] = 0; 
    2 : dout[1] = 1; 
    4 : dout[2] = 2; 
    8 : dout[3] = 3; 
    default : dout = 2’bxx;
endcase 
endmodule
//Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; din=1; 
#100; din=2; 
#100; din=4; 
#100; din=8;
end
initial begin 
#100 
$monitor(“din=%b, dout=%b”, din, dout); 
end 
endmodule

Xillinx Output:

Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code
4 - 2 Encoder Behavioral Modelling Verilog Response

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