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Verilog: 8 to 1 Multiplexer (8-1 MUX) Dataflow Modelling with Testbench Code

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 Verilog Code for 8 to 1 Multiplexer Dataflow Modelling 

module mux_8to1( 
 
input a,

input b,

input c,

input D0,

input D1,

input D2,

input D3,

input D4,

input D5,

input D6,

input D7,

output out,

);


module m81(output
out, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);

assign S1bar=~S1;
assign S0bar=~S0;
assign S2bar=~S2;
assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & S0) | (D2 & S2bar & S1 & S0bar) + (D3
 & S2bar & S1 & S0) + (D4 & S2 & S1bar & S0bar) + (D5 & S2 & S1bar & S0) + (D6 & S2 & S1 & S0bar) + (D7 &
 S2 & S1 & S0);

endmodule


//Testbench code for 8-1 MUX Dataflow Modelling
 initial begin

// Initialize Inputs

a= 0;b = 0;c = 0;D0 = 1;D1 = 0;D2 = 0;D3 = 0;D4 = 0;D5 = 0;D6 = 0;D7 = 0;

// Wait 100 ns for global reset to finish

 #100;

// Add stimulus here
#100; a = 0;b = 0;c = 1;d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100; a = 0;b = 1;c = 0;d0 = 0;d1 = 0;d2= 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100;a = 0;b = 1;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#100;a = 1;b = 0;c = 0;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;d7 = 0;
#100;a = 1;b = 0;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 1;d6 = 0;d7 = 0; 
#100;a = 1;b = 1;c = 0;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 1;d7 = 0;
#100;a = 1;b = 1;c = 1;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 1;  
end

Xillinx Output:

8 to 1 Multiplexer Dataflow Modelling


8-1 MUX Dataflow Modelling

Also See:

List of Verilog Programs

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