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Verilog: 4 to 1 Multiplexer Behavioral Modelling with Testbench Code

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Verilog Code 4-1 Multiplexer Behavioral Modelling using Case Statement

module Mux_4to1 (
input [3:0]i, 
input s1, s0, 
output out
);


always @(i or s1 or s0) 

case({s1, s0})

0 : out = i[0]; 


1 : out = i[1];

2 : out = i[2];

3 : out = i[3];
default : out = 1’bx;

endcase
endmodule

//test-bench 
initial begin
i=1'b1010; s1=0; s0=0;

#100;

//wait 100ns for global reset to finish
//add stimulus here
#100 s1 = 0; s0= 1;
#100 s1 = 1; s0= 0;
#100 s1 = 1; s0= 1;

end

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