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Verilog: 4 - 2 Encoder Structural/Gate Level Modelling with Testbench
Verilog Code for 4-2 Encoder Structural/Gate Level Modelling module encode_4_to_2( input d0,d1,d2,d3, output a0,a1 ); wire x,y,z; not g1(x,d2); and g2(y,x,d1); or g3(a0,y,d3); or g4(a1,d2,d3); endmodule //Testbench code for 4-2 Encoder Structural/Gate Level Modelling initial begin // Initialize Inputs d0 = 1;d1 = 0;d2 = 0;d3 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0; #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1; end Output: Verilog 4-2 Encoder Response Other Verilog Programs: Go to Index of Verilog Programming
Verilog Code for 1 to 8 DEMUX with Testbench Code
Verilog Code for 1-8 DEMUX Structural/Gate Level Modelling module demux_1_to_8( input d, input s0, input s1, input s2, output y0, output y1, output y2, output y3, output y4, output y5, output y6, output y7 ); not (s0n,s0),(s1n,s1),(s2n,s2); and (y0,d,s0n,s1n,s2n),(y1,d,s0,s1n,s2n),(y2,d,s0n,s1,s2n),(y3,d,s0,s1,s2n),(y4,d,s0n,s1n,s2),(y5,d,s0,s1n,s2),(y6,d,s0n,s1,s2),(y7,d,s0,s1,s2); endmodule //Testbench code for 1-8 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 0;s0 = 0;s1 = 0;s2 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; d = 1;s0 = 0;s1 = 0;s2 = 0; #100; d = 1;s0 = 1;s1 = 0;s2 = 0; #100; d = 1;s0 = 0;s1 = 1;s2 = 0; #100; d = 1;s0 = 1;s1 = 1;s2 = 0; #100; d = 1;s0 = 0;s1 = 0;s2 = 1; #100; d = 1;s0 = 1;s1 = 0;s2 = 1; #100; d = 1;s0 = 0;s1 = 1;s2 = 1; #100; d = 1;s0 = 1;s1 = 1;s2 = 1; end Output: Verilog/VLSI 1-8
Verilog: 8-3 Encoder Structural/Gate Level Modelling with Testbench
Verilog Code for 8-3 Encoder Structural/Gate Level Modelling module encoder_8_to_3( input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, output q0, output q1, output q2 ); or (q0,d1,d3,d5,d7),(q1,d2,d3,d6,d7),(q2,d4,d5,d6,d7); endmodule //Testbench code for 8-3 Encoder Structural/Gate Level Modelling initial begin // Initialize Inputs d0 = 1; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;
Verilog: Binary to Gray Converter Structural/Gate Level Modelling with Testbench
Verilog Code for Binary to Gray Structural/Gate Level Modelling module binary_to_gray( input b1, input b2, input b3, input b4, output g1, output g2, output g3, output g4 ); buf(g1,b1); xor (g2,b1,b2),(g3,b2,b3),(g4,b3,b4); endmodule //Testbench code for Binary to Gray Structural/Gate Level Modelling initial begin // Initialize Inputs b1 = 0;b2 = 0;b3 = 0;b4 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;b1 = 0;b2 = 0;b3 = 0;b4 = 1; #100;b1 = 0;b2 = 0;b3 = 1;b4 = 0; #100;b1 = 0;b2 = 0;b3 = 1;b4 = 1; #100;b1 = 0;b2 = 1;b3 = 0;b4 = 0; #100;b1 = 0;b2 = 1;b3 = 0;b4 = 1; #100;b1 = 0;b2 = 1;b3 = 1;b4 = 0; #100;b1 = 0;b2 = 1;b3 = 1;b4 = 1; #100;b1 = 1;b2 = 0;b3 = 0;b4 = 0; #100;b1 = 1;b2 = 0;b3 = 0;b4 = 1; #100;b1 = 1;b2 = 0;b3 = 1;b4 = 0; #100;b1 = 1;b2 = 0;b3 = 1;b4 = 1; #100;b1 = 1;b2 = 1;b3 = 0;b4 = 0; #100;b1 = 1;b2 = 1;b3 = 0;b4 = 1; #100;b1 = 1;b2 = 1;b3 = 1;b4 = 0; #100;b1 = 1;b2 = 1;b3
Verilog: Gray to Binary Converter Structural/Gate Level Modelling with Testbench
Verilog Code for Gray to Binary Structural/Gate Level Modelling module gray_to_binary( input g0, input g1, input g2, input g3, output b0, output b1, output b2, output b3 ); buf(b0,g0); xor (b1,g0,g1),(b2,g0,g1,g2),(b3,g0,g1,g2,g3); endmodule //Testbench code for Gray to Binary Structural/Gate Level Modelling initial begin // Initialize Inputs g0 = 0;g1 = 0;g2 = 0;g3 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #50;g0 = 0;g1 = 0;g2 = 0;g3 = 1; #50;g0 = 0;g1 = 0;g2 = 1;g3 = 0; #50;g0 = 0;g1 = 0;g2 = 1;g3 = 1; #50;g0 = 0;g1 = 1;g2 = 0;g3 = 0; #50;g0 = 0;g1 = 1;g2 = 0;g3 = 1; #50;g0 = 0;g1 = 1;g2 = 1;g3 = 0; #50;g0 = 0;g1 = 1;g2 = 1;g3 = 1; #50;g0 = 1;g1 = 0;g2 = 0;g3 = 0; #50;g0 = 1;g1 = 0;g2 = 0;g3 = 1; #50;g0 = 1;g1 = 0;g2 = 1;g3 = 0; #50;g0 = 1;g1 = 0;g2 = 1;g3 = 1; #50;g0 = 1;g1 = 1;g2 = 0;g3 = 0; #50;g0 = 1;g1 =
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming
Verilog: 1 to 2 DEMUX (Demultiplexer) Structural/Gate Level Modelling with Testbench
Verilog Code for 1-2 DEMUX Structural/Gate Level Modelling 1-2 DEMUX module DEMUX_1_to_2( input s, input d, output y0, output y1 ); not(sn,s); and(y0,sn,d); and(y1,s,d); endmodule //Testbench code for 1-2 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs s = 0; d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s=0;d=1; #100; s=1;d=0; #100; s=1;d=1; end Output: Verilog 1-2 DEMUX Response Other Verilog Programs: Go to Index of Verilog Programming
VLSI: 3-8 Decoder Structural/Gate Level Modelling with Testbench
Verilog Code for 3-8 Decoder Structural/Gate Level Modelling 3-8 Line Decoder module decoder3_to_8( input x, input y, input z, output d0, output d1, output d2, output d3, output d4, output d5, output d6, output d7 ); and (d0,xn,yn,zn),(d1,xn,yn,z),(d2,xn,y,zn),(d3,xn,y,z),(d4,x,yn,zn),(d5,x,yn,z),(d6,x,y,zn),(d7,x,y,z); not (xn,x),(yn,y),(zn,z); endmodule //Testbench code for 3-8 Decoder Structural/Gate Level Modelling initial begin // Initialize Inputs x = 0;y = 0;z = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;x = 0;y = 0;z = 1; #100;x = 0;y = 1;z = 0; #100;x = 0;y = 1;z = 1; #100;x = 1;y = 0;z = 0; #100;x = 1;y = 0;z = 1; #100;x = 1;y = 1;z = 0; #100;x = 1;y = 1;z = 1; end Output: Verilog 3-8 Decoder Response Other Verilog Programs: Go to Index of Verilog Programming
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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s0=0;s1=1;a=0;b=1;c=0;d=0; #100; s0=1;s1=0;a=0;b=0;c=1;d=0;
VLSI: Half Subtractor and Full Subtractor Gate Level Modelling
Half Subtractor: Verilog Module Code: module half_subtractor ( input a, input b, output diff output borr ); wire x; xor (diff,a,b); not (x,a); and (borr,x,b); endmodule Full Subtractor: Verilog Module Code: module full_subtractor ( input a, input b, input c, output diff output borr ); wire x,n2,z,n1; xor s1(x,a,b); not s3(n2,x); not s4(n1,c); and s5(y,n1,b); xor s2(diff,a,x); and s6(z,n2,a); or (borr,y,z); endmodule
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming