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Verilog: 4 Bit Full Adder Behavioral Modelling with Testbench Code

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Verilog Code for 4 Bit Full Adder Behavioral Modelling with Testbench Code

module 4_bit_Add(
    input [3:0]a,b,
    input cin, 
    output [3:0]sum,
    output cout 
    );
reg [3:0]sum; 
reg cout; 
 
always @ (a or b or cin)
   assign {cout,sum}= a + b + cin;
endmodule
//Testbench code for 4 Bit Full Adder Behavioral Modelling 
initial begin
// Initialize Inputs 
a = 0; b = 0; cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100 a=4; b=9; cin=1; 
#100 a=15; b=5; cin=1; 
#100 a=7; b=5; cin=0; 
#100 a=6; b=10; cin=1;  
end
initial begin 
#100 
$monitor(“a = %b, b = %b, cin = %b, sum = %b, cout = %b”, a, b, cin, sum, cout); 
end 
endmodule

Xillinx Output:

4 Bit Full Adder Behavioral Modelling
4 Bit Full Adder Behavioral Modelling Response

Also See:

List of Verilog Programs

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